Presentation	1999/6/11 Circuit and Layout Optimization for Dynamic CMOS Cells with Two Pairs of Power Lines I : Domino CMOS "Quasi-Standard-Cell" Layout Toshiro Akino,
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Abstract(in English)	As system-LSI's are currently in a mass production by even early adopting 0.18μm bulk CMOS process, standard-cell libraries with low power-consumption and high clock-frequency are increasingly in great demand. We insist to develop dynamic CMOS cell libraries with two pairs of the conventional power lines [V_ , V_] and additional substrate-bias power lines [V_(>V_ ), V_()]. In this paper I, focusing on domino CMOS circuits, we propose an architecture of "quasi-standard-cell" layout with two kinds of rows with electrically separated substrates, where one consists of the logic circuits having a low V_T and the other does the clock-driven pull-up/pull-down and output-driven inverter ciucuits having a high V_T.
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Keyword(in English)	two power lines / substrate-bias / standard-cell libraties / domino CMOS circuits
Paper #	VLD99-34
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Conference Information
Committee	VLD
Conference Date	1999/6/11(1days)
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Paper Information
Registration To	VLSI Design Technologies (VLD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Circuit and Layout Optimization for Dynamic CMOS Cells with Two Pairs of Power Lines I : Domino CMOS "Quasi-Standard-Cell" Layout
Sub Title (in English)
Keyword(1)	two power lines
Keyword(2)	substrate-bias
Keyword(3)	standard-cell libraties
Keyword(4)	domino CMOS circuits
1st Author's Name	Toshiro Akino
1st Author's Affiliation	Department of Electronic System and Information Engineering School of Biology-Oriented Science and Technology, Kinki University()
Date	1999/6/11
Paper #	VLD99-34
Volume (vol)	vol.99
Number (no)	108
Page	pp.pp.-
#Pages	7
Date of Issue