| Presentation | 1999/6/11 A Hardware Architecture of Motion Estimator with 8x8 Block Mode for MPEG4 and Its VHDL Model Kenji SAKAMOTO, Shogo MURAMATSU, Hitoshi KIYA, Akihiko YAMADA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In MPEG4, a new moving picture coding standard, there both 16×16 block mode and 8×8 block mode. In this report, we propose a linear array architecture of motion estimatior with 8×8 block mode. The proposed architecture is improved in both the internal of processing elements (PE) and comparator module from the conventional one. The input is the same as the conventional one. In the internal of PE, some multiplexers and an accumulater are added to the convetional architecture. The improvement of the conventional PE makes it possible to select and accumulate the sum of absolute differences (SAD) in the 8×8 block mode. Since the output timing of SAD in the 8×8 block mode differs from that of 16×16 block mode, This paper proposes two architecture for the 8×8 block mode. The verify the significance for VLSI implementation, the performance is estimated by using the synthesis result of the VHDL. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MPEG4 / Motion estimation / Block matching / Linear array architecture |
| Paper # | VLD99-31 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1999/6/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Hardware Architecture of Motion Estimator with 8x8 Block Mode for MPEG4 and Its VHDL Model |
| Sub Title (in English) | |
| Keyword(1) | MPEG4 |
| Keyword(2) | Motion estimation |
| Keyword(3) | Block matching |
| Keyword(4) | Linear array architecture |
| 1st Author's Name | Kenji SAKAMOTO |
| 1st Author's Affiliation | Dept. of Electrical Eng., Graduate School of Eng., Tokyo Metropolitan Univ.() |
| 2nd Author's Name | Shogo MURAMATSU |
| 2nd Author's Affiliation | Dept. of Electrical Eng., Graduate School of Eng., Tokyo Metropolitan Univ. |
| 3rd Author's Name | Hitoshi KIYA |
| 3rd Author's Affiliation | Dept. of Electrical Eng., Graduate School of Eng., Tokyo Metropolitan Univ. |
| 4th Author's Name | Akihiko YAMADA |
| 4th Author's Affiliation | Dept. of Electrical Eng., Graduate School of Eng., Tokyo Metropolitan Univ. |
| Date | 1999/6/11 |
| Paper # | VLD99-31 |
| Volume (vol) | vol.99 |
| Number (no) | 108 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |