| Presentation | 1999/6/10 A VLSI Architecture of Median-Cut Quantization for Low-Bit Motion Estimation Shogo MURAMATSU, Hitoshi KIYA, Akihiko YAMADA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this work, a bit-operation algorithm for the median-cut quantization (MCQ) is proposed and then the VLSI architecture is provided for low-bit block matching motion estimation. MCQ is the thechnique that reduces multi-valued samples to binary-valued ones by adaptively taking the median value as the threshold. In the proposed method, the search process of the median value is derived from the quick-sort algorithm. Samples are quantized during the search process. Firstly, the bit-serial procedure is shown, and then it is modified to the bit-parallel procedure. The extension to the multi-level quantization is also discussed. Since the proposed algorithm is based on bit poerations, it is suitable for the VLSI implementation. To verify the significance, for the application to the motion estimation, the performance is estimated from the synthesis result of the VHDL model. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Adaptive quantization / Median value / VLSI architecture / Motion estimation / MPEG |
| Paper # | VLD99-29 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1999/6/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A VLSI Architecture of Median-Cut Quantization for Low-Bit Motion Estimation |
| Sub Title (in English) | |
| Keyword(1) | Adaptive quantization |
| Keyword(2) | Median value |
| Keyword(3) | VLSI architecture |
| Keyword(4) | Motion estimation |
| Keyword(5) | MPEG |
| 1st Author's Name | Shogo MURAMATSU |
| 1st Author's Affiliation | Dept. of Electrical Eng., Graduate School of Eng., Tokyo Metropolitan Univ.() |
| 2nd Author's Name | Hitoshi KIYA |
| 2nd Author's Affiliation | Dept. of Electrical Eng., Graduate School of Eng., Tokyo Metropolitan Univ. |
| 3rd Author's Name | Akihiko YAMADA |
| 3rd Author's Affiliation | Dept. of Electrical Eng., Graduate School of Eng., Tokyo Metropolitan Univ. |
| Date | 1999/6/10 |
| Paper # | VLD99-29 |
| Volume (vol) | vol.99 |
| Number (no) | 107 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |