| Presentation | 1998/9/22 On the Test Sequence Compaction for Acyclic Sequential Circuits Using Time-Expansion Model Toshinori Hosokawa, Tomoo Inoue, Toshihiro Hiraoka, Hideo Fujiwara, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we present a static test sequence compaction method for acyclic sequential circuits using a template which is a test sequence represented by two values, b (0 or 1) and x (don't care) and a dynamic test sequence compaction method for acyclic sequential circuits by performing a reverse transformation fault simulation. A template for the static test sequence compaction method is generated by compacting some primitive templates which are uniquely determined from a time-expansion model. We formulate a optimization problem to maximize the number of primitive templates to be compacted into the template with a certain length on the template generation for the static test sequence compaction and present a heuristic algorithm for the problem. We evaluate our methods using practical circuits and show that our methods are effective. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Time-Expansion / Acyclic Sequential Circuits / Primitive Template / Test Sequence Compaction / Test Sequence Transformation / Reverse Transformation Fault Simulation / Template |
| Paper # | VLD98-64,ICD98-167,FTS98-91 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1998/9/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On the Test Sequence Compaction for Acyclic Sequential Circuits Using Time-Expansion Model |
| Sub Title (in English) | |
| Keyword(1) | Time-Expansion |
| Keyword(2) | Acyclic Sequential Circuits |
| Keyword(3) | Primitive Template |
| Keyword(4) | Test Sequence Compaction |
| Keyword(5) | Test Sequence Transformation |
| Keyword(6) | Reverse Transformation Fault Simulation |
| Keyword(7) | Template |
| 1st Author's Name | Toshinori Hosokawa |
| 1st Author's Affiliation | Corporate Semiconductor Development Division, Matsushita Electric Industrial Co., Ltd.() |
| 2nd Author's Name | Tomoo Inoue |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Toshihiro Hiraoka |
| 3rd Author's Affiliation | Corporate Semiconductor Development Division, Matsushita Electric Industrial Co., Ltd. |
| 4th Author's Name | Hideo Fujiwara |
| 4th Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| Date | 1998/9/22 |
| Paper # | VLD98-64,ICD98-167,FTS98-91 |
| Volume (vol) | vol.98 |
| Number (no) | 287 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |