| Presentation | 1998/9/22 VLSI Implementation of a Recursive Maximum Likelihood Decoder dedicated to High-Speed Satellite Communication Daisuke TAKI, Morgan Hirosuke Miki, Gen FUJITA, Takao ONOYE, Isao SHIRAKAWA, Toru FUJIWARA, Tadao KASAMI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A decoder of (64, 35) Reed-Muller subcode has been implemented, dedicatedly for high-speed satellite communication. The trellis-based recursive maximum likelihood decoding algorithm, which greatly reduces computational costs of the conventional Viterbi algorithm, is integrated in a single chip by using 3-stage pipeline architecture of add-compare-select tree. By using 0.6 μm CMOS triple-metal technology, the (64, 35) decoder is implemented with 202, 550 gates and operates at 60MHz of clock rate. The 600Mbps (64, 40) decoding system required for satellite communication can be constructed by employing 32 proposed decoders in parallel. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Reed-Muller code / recursive maximum likelihood decoding algorithm / satellite communication system / trellis diagram |
| Paper # | VLD98-52,ICD98-155,FTS98-79 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1998/9/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | VLSI Implementation of a Recursive Maximum Likelihood Decoder dedicated to High-Speed Satellite Communication |
| Sub Title (in English) | |
| Keyword(1) | Reed-Muller code |
| Keyword(2) | recursive maximum likelihood decoding algorithm |
| Keyword(3) | satellite communication system |
| Keyword(4) | trellis diagram |
| 1st Author's Name | Daisuke TAKI |
| 1st Author's Affiliation | Dept. Info. Sys. Eng., Osaka Univ.() |
| 2nd Author's Name | Morgan Hirosuke Miki |
| 2nd Author's Affiliation | Dept. Info. Sys. Eng., Osaka Univ. |
| 3rd Author's Name | Gen FUJITA |
| 3rd Author's Affiliation | Dept. Info. Sys. Eng., Osaka Univ. |
| 4th Author's Name | Takao ONOYE |
| 4th Author's Affiliation | Dept. Info. Sys. Eng., Osaka Univ. |
| 5th Author's Name | Isao SHIRAKAWA |
| 5th Author's Affiliation | Dept. Info. Sys. Eng., Osaka Univ. |
| 6th Author's Name | Toru FUJIWARA |
| 6th Author's Affiliation | Dept. Info. and Math. Science, Osaka Univ. |
| 7th Author's Name | Tadao KASAMI |
| 7th Author's Affiliation | Faculty of Information Sciences Hiroshima City Univ. |
| Date | 1998/9/22 |
| Paper # | VLD98-52,ICD98-155,FTS98-79 |
| Volume (vol) | vol.98 |
| Number (no) | 287 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |