| Presentation | 1998/9/21 Self-Timed Implementation of Boolean Functions Saarepera Mart, Tomohiro Yoneda, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Since asynchronous circuits have no clock, the completion of the computation must be notified by using some special ways. There exists a class of asynchronous circuits which generate such completion signals by themselves. These circuits function under a signaling scheme called protocol. In this paper, we discuss how to implement such a class of asynchronous circuits. In the previous works, the implementation of such circuits needs asynchronous automata which make the circuits complicated and slow. In this paper, we propose a new protocol which guarantees that environment can correctly know the completion of the computation, and show that circuits which satisfy the protocol can be implemented without involving asynchronous automata. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Asynchronous combinational circuits / delay-insensitivity / protocol |
| Paper # | VLD98-43,ICD98-146,CPSY98-80,FTS98-70 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1998/9/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Self-Timed Implementation of Boolean Functions |
| Sub Title (in English) | |
| Keyword(1) | Asynchronous combinational circuits |
| Keyword(2) | delay-insensitivity |
| Keyword(3) | protocol |
| 1st Author's Name | Saarepera Mart |
| 1st Author's Affiliation | Department of Computer Science Tokyo Institute of Technology() |
| 2nd Author's Name | Tomohiro Yoneda |
| 2nd Author's Affiliation | Department of Computer Science Tokyo Institute of Technology |
| Date | 1998/9/21 |
| Paper # | VLD98-43,ICD98-146,CPSY98-80,FTS98-70 |
| Volume (vol) | vol.98 |
| Number (no) | 286 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |