Presentation 1998/9/21
Overview of Adaptive Device RHW and Its Mapping Methods
Tsukasa YAMAUCHI, Shougo NAKAYA, Takeshi INUO, Nobuki KAJIHARA,
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Abstract(in English) Conventional microprocessors show poor performance in real world applications, such as image processing, characteristics extraction from huge number of patterns and real time processing. Therfore we decided to develop a novel reconfigurable adaptive device prototype chip that is a new generation FPGA and achieves high performance by mapping target algorithms directly on its reconfigurable architecure. We have developed a prototype chips, RHW to prove feasibility and performance of proposed architecture. In this paper, we describe overview of the prototype chip and its mapping environment.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) reconfigurable computing / FPGA / logic synthesis / routing
Paper # VLD98-42,ICD98-145,CPSY98-79,FTS98-69
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Committee VLD
Conference Date 1998/9/21(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Overview of Adaptive Device RHW and Its Mapping Methods
Sub Title (in English)
Keyword(1) reconfigurable computing
Keyword(2) FPGA
Keyword(3) logic synthesis
Keyword(4) routing
1st Author's Name Tsukasa YAMAUCHI
1st Author's Affiliation RWCP Adaptive Devices NEC Laboratory()
2nd Author's Name Shougo NAKAYA
2nd Author's Affiliation RWCP Adaptive Devices NEC Laboratory
3rd Author's Name Takeshi INUO
3rd Author's Affiliation RWCP Adaptive Devices NEC Laboratory
4th Author's Name Nobuki KAJIHARA
4th Author's Affiliation RWCP Adaptive Devices NEC Laboratory
Date 1998/9/21
Paper # VLD98-42,ICD98-145,CPSY98-79,FTS98-69
Volume (vol) vol.98
Number (no) 286
Page pp.pp.-
#Pages 8
Date of Issue