| Presentation | 1998/12/10 A Simultaneous Placement and Global Routing Algorithm for FPGAs with Macro-Blocks Daisuke INOUE, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A macro-block of FPGAs is a set preplaced and prerouted logic-blocks which can imprement a logic function such as an adder or a multiplier. Macro-blocks are indispensable to increase the clock freqency and also logic-block utilization of an FPGA chip. This paper proposes a simultaneous placement and grobal routing algorithm for FPGAs with macro-blocks. The algorithm consists of top-down partitioning and bottom-up combining. The top-down partitioning phase is based on hierarchical bipartitioning of a layout region and a set of macro-block. If there exist connections between bipartitioned macroblock sets, pseudo-pins are introduced to perserve the connections. In this phase rough information for macro-block placement and global routing can be obtained. The Bottom-up combining phase combines partitioned layout regions and macro-blocks and determines datailed placement. The experimental results demonstrate the efficiency and effectiveness of the algorithm. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / macro-block / simultaneous placement and routing / top-down partitioning / bottom-up combining |
| Paper # | VLD98-115,CPSY98-135 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1998/12/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Simultaneous Placement and Global Routing Algorithm for FPGAs with Macro-Blocks |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | macro-block |
| Keyword(3) | simultaneous placement and routing |
| Keyword(4) | top-down partitioning |
| Keyword(5) | bottom-up combining |
| 1st Author's Name | Daisuke INOUE |
| 1st Author's Affiliation | Dept. of Electronics, Information and Communication Engineering Waseda University() |
| 2nd Author's Name | Nozomu TOGAWA |
| 2nd Author's Affiliation | Dept. of Electronics, Information and Communication Engineering Waseda University |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Dept. of Electronics, Information and Communication Engineering Waseda University |
| 4th Author's Name | Tatsuo OHTSUKI |
| 4th Author's Affiliation | Dept. of Electronics, Information and Communication Engineering Waseda University |
| Date | 1998/12/10 |
| Paper # | VLD98-115,CPSY98-135 |
| Volume (vol) | vol.98 |
| Number (no) | 446 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |