Presentation 1998/12/10
A Synthesis Method for Asynchronous Logic Circuits on Array of LUTs
Ryusuke Konishi, Kiyoshi Oguri, Hideyuki Ito, Kouichi Nagami,
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Abstract(in English) Asynchronous circuit design has been said to be an effective solution to avoid clock-skew problem. On the other hand, with high-level design methods using HDL, synchronous models are easier understrood than asynchronous ones. To bridge this gap, we propose a transformation method from synchronous to asynchronous circuits. We show that the sequence of data-processing of the generated asynchonous circuits, is the same as that of the original synchronous ones. Using this method, we are aiming to execute conventional synchronous desciption based models as asynchronous circuits implemented on a regular LUT conventional synchronous description based models as asynchronous circuits implemented on a regular LUT array.
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Keyword(in English) Asynchronous circuits / Logic synthesis / Petri-net / FPGA / PCA
Paper # VLD98-113,CPSY98-133
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Committee VLD
Conference Date 1998/12/10(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Synthesis Method for Asynchronous Logic Circuits on Array of LUTs
Sub Title (in English)
Keyword(1) Asynchronous circuits
Keyword(2) Logic synthesis
Keyword(3) Petri-net
Keyword(4) FPGA
Keyword(5) PCA
1st Author's Name Ryusuke Konishi
1st Author's Affiliation NTT Optical Network Systems Laboratories()
2nd Author's Name Kiyoshi Oguri
2nd Author's Affiliation NTT Optical Network Systems Laboratories
3rd Author's Name Hideyuki Ito
3rd Author's Affiliation NTT Optical Network Systems Laboratories
4th Author's Name Kouichi Nagami
4th Author's Affiliation NTT Optical Network Systems Laboratories
Date 1998/12/10
Paper # VLD98-113,CPSY98-133
Volume (vol) vol.98
Number (no) 446
Page pp.pp.-
#Pages 8
Date of Issue