Presentation 1998/12/10
A Method for Synthesizing LUT Networks Integrating Various Decomposition Methods
Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya,
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Abstract(in English) This paper presents a method for synthesizing look-up table (LUT) networks. The strategy employed by our method is very different from the strategies of previous methods ; many decomposition methods that are not only algebraic but also functional are integrated every well. To select a possibly best decomposition form for an intermediate decomposition, we use a cost data base file which is generated from the previous decomposed networks.Our method can be thought of as a general framework for LUT network synthesis integrating various decomposition methods. The experimental results are very encouraging.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) functional decomposition / algebraic decomposition / field programmable gate array (FPGA) / look-up table (LUT)
Paper # VLD98-111,CPSY98-131
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Committee VLD
Conference Date 1998/12/10(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Method for Synthesizing LUT Networks Integrating Various Decomposition Methods
Sub Title (in English)
Keyword(1) functional decomposition
Keyword(2) algebraic decomposition
Keyword(3) field programmable gate array (FPGA)
Keyword(4) look-up table (LUT)
1st Author's Name Shigeru Yamashita
1st Author's Affiliation NTT Communication Science Laboratoeies()
2nd Author's Name Hiroshi Sawada
2nd Author's Affiliation NTT Communication Science Laboratoeies
3rd Author's Name Akira Nagoya
3rd Author's Affiliation NTT Communication Science Laboratoeies
Date 1998/12/10
Paper # VLD98-111,CPSY98-131
Volume (vol) vol.98
Number (no) 446
Page pp.pp.-
#Pages 8
Date of Issue