Presentation | 1998/12/10 A Realization of Cycle-based Simulation Engine Atsumu ISENO, Yukihiro IGUCHI, Tsutomu SASAO, Munehiro MATSUURA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | We propose a cycle-based simulation engine, which is based on a software cycle-based simulator. This engine consists of RAMs and control circuits. BDD data are stored in RAMs. The control circuits, which are implemented in FPGAs, trace the edges according to input vectors. We accelerate it by pipelining. Preliminary experimental results show that a non-pipelined simulation engine is about 2~4 times faster, and a pipelined one is about 10n times faster than a software cycle-based simulator, where n is the number of inputs. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Logic simulation / Simulation engine / BDD / FPGA |
Paper # | VLD98-109,CPSY98-129 |
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Committee | VLD |
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Conference Date | 1998/12/10(1days) |
Place (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Realization of Cycle-based Simulation Engine |
Sub Title (in English) | |
Keyword(1) | Logic simulation |
Keyword(2) | Simulation engine |
Keyword(3) | BDD |
Keyword(4) | FPGA |
1st Author's Name | Atsumu ISENO |
1st Author's Affiliation | Dept. of Computer Science Meiji University() |
2nd Author's Name | Yukihiro IGUCHI |
2nd Author's Affiliation | Dept. of Computer Science Meiji University |
3rd Author's Name | Tsutomu SASAO |
3rd Author's Affiliation | Dept. of Electronics and Computer Science Kyusyu Institute of Technology |
4th Author's Name | Munehiro MATSUURA |
4th Author's Affiliation | Dept. of Electronics and Computer Science Kyusyu Institute of Technology |
Date | 1998/12/10 |
Paper # | VLD98-109,CPSY98-129 |
Volume (vol) | vol.98 |
Number (no) | 446 |
Page | pp.pp.- |
#Pages | 8 |
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