| Presentation | 1998/12/10 Design of Digital Signal Processing FPGA Architecture Using New Redundant Number Representation Yoshiki SAWADA, Takafumi AOKI, Tatsuo HIGUCHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents "Signed-Weight Number System (SW Number System)", which is useful for designing high-speed multiply-add modules for digital signal processing applications. The SW number system makes possible the unified representation of positive and negative numbers by adjusting the signs of individual digit positions. Compared with the conventional two's complement representation, the SW nymber representation, the SW number representation makes possible the constuction of highly regular arithmetic circuits without introducing irregular arithmetic operations, such as sign extension and LSB compensation. This paper also presents the design of a Field Programmable Digital Filter (FPDF) IC-a special-purpose FPGA for high-speed FIR filtering-based on the proposed SW arithmetic. The result of the experimental fabrication of test circuits is also described. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Computer arithmetic / Digital Filter / Multiply-add operations / VLSI |
| Paper # | VLD98-107,CPSY98-127 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1998/12/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Digital Signal Processing FPGA Architecture Using New Redundant Number Representation |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Computer arithmetic |
| Keyword(3) | Digital Filter |
| Keyword(4) | Multiply-add operations |
| Keyword(5) | VLSI |
| 1st Author's Name | Yoshiki SAWADA |
| 1st Author's Affiliation | Graduate School of Information Sciences, Tohoku University() |
| 2nd Author's Name | Takafumi AOKI |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 3rd Author's Name | Tatsuo HIGUCHI |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| Date | 1998/12/10 |
| Paper # | VLD98-107,CPSY98-127 |
| Volume (vol) | vol.98 |
| Number (no) | 446 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |