| Presentation | 1998/12/10 A Reciprocal Number Calculation Circuit Design for FPGA W Ogata, H Kasahara, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | There are two major approaches to evaluate new computer architesture, the evaluation with software emulator on WS or high-performance PC. The other is the evaluation on hardware emulator. However, it takes very long time on the evaluation with the software emulator to new architecture using large benchmark programs. On the other hand, it is expensive to develop a machine. Also, it takes long time to develop new machine. Even if we have hardware, it is very difficult to modify it. So, evaluation of different architecture is difficult by using the same hardware. To cope with these problems, we have been developed an architecture emulator, which is high-performance with floating point arithmetic unit ; not so expensive cost, reconfigurable easily. It is combination of S-RAM based large scale FPGAs (Field Programmable Gate Array). During the execution of real-benchmark program, many amount of floating division operation may be executed. So we have designed a reciprocal number calculation circuit considering the feature of FPGAs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Floating-Point Calculation / FPGA / Emulation / Evaluation / Benchmark / Computer-Architecture |
| Paper # | VLD98-106,CPSY98-126 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1998/12/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Reciprocal Number Calculation Circuit Design for FPGA |
| Sub Title (in English) | |
| Keyword(1) | Floating-Point Calculation |
| Keyword(2) | FPGA |
| Keyword(3) | Emulation |
| Keyword(4) | Evaluation |
| Keyword(5) | Benchmark |
| Keyword(6) | Computer-Architecture |
| 1st Author's Name | W Ogata |
| 1st Author's Affiliation | Department of Electrical, Electronics and Computer Engineering, Waseda University() |
| 2nd Author's Name | H Kasahara |
| 2nd Author's Affiliation | Department of Electrical, Electronics and Computer Engineering, Waseda University |
| Date | 1998/12/10 |
| Paper # | VLD98-106,CPSY98-126 |
| Volume (vol) | vol.98 |
| Number (no) | 446 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |