Presentation 1998/12/10
A Study on a Reconfigurable Synchronous Dataflow Computer
Hiroshi Sasaki, Hideaki Tsukioka, Nobuyoshi Shoji, Hiroaki Kobayashi, Tadao Nakamura,
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Abstract(in English) This report proposes a synchronous dataflow computer, which constructs hardware to represent dataflow graphs of applications then processes data in the dataflow fashion. We implemented JPEG encoder on the system and measured the amount of required hardware resources. The experimental results show that computations can naturally be expressed in datafolw graphs using units only for accessing the shared memory. The exploitable features of applications are discussed and a software development environment is also presented.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Reconfigurable / Synchronous / Dataflow / Computer
Paper # VLD98-101,CPSY98-121
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Conference Information
Committee VLD
Conference Date 1998/12/10(1days)
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Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Study on a Reconfigurable Synchronous Dataflow Computer
Sub Title (in English)
Keyword(1) Reconfigurable
Keyword(2) Synchronous
Keyword(3) Dataflow
Keyword(4) Computer
1st Author's Name Hiroshi Sasaki
1st Author's Affiliation ()
2nd Author's Name Hideaki Tsukioka
2nd Author's Affiliation
3rd Author's Name Nobuyoshi Shoji
3rd Author's Affiliation
4th Author's Name Hiroaki Kobayashi
4th Author's Affiliation
5th Author's Name Tadao Nakamura
5th Author's Affiliation
Date 1998/12/10
Paper # VLD98-101,CPSY98-121
Volume (vol) vol.98
Number (no) 446
Page pp.pp.-
#Pages 6
Date of Issue