Presentation 1998/12/10
A Hardware System of Self-Reconfigurable 2D-Mesh Multiprocessor
Junya Yamada, Toru Abe, Susumu Horiguchi,
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Abstract(in English) To achieve high-performance computing for large scale advanced applications, many researchers have been studying massively parallel computers consisting of a large number of processing elements (PEs). A Fault-tolerance is one of the critical problems to construct massively parallel computers. Several reconfiguration architectures using spare PEs, tracks and switches have been proposed for 2D-mesh multiprocessor systems. Several reconfiguration schemes of 2D-mesh array theoretically discussed by only simulations. However, a hardware implementation of the reconfiguration algorithms to achieve fault-tolerance have not been studied yet. We propose new hardware systems to achieve self-reconfiguration of 2D-mesh multiprocessor systems. The hardware systems are implemented on FPGAs and evaluated on reconfiguration times and the number of gates required for redundant circuits.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) 2D-mesh Array / Self-Reconfiguration / Defect Avoidance / Fault Tolerance / FPGA
Paper # VLD98-99,CPSY98-119
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Conference Information
Committee VLD
Conference Date 1998/12/10(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Hardware System of Self-Reconfigurable 2D-Mesh Multiprocessor
Sub Title (in English)
Keyword(1) 2D-mesh Array
Keyword(2) Self-Reconfiguration
Keyword(3) Defect Avoidance
Keyword(4) Fault Tolerance
Keyword(5) FPGA
1st Author's Name Junya Yamada
1st Author's Affiliation School of Information Science Japan Advanced Institute of Science and Technology()
2nd Author's Name Toru Abe
2nd Author's Affiliation School of Information Science Japan Advanced Institute of Science and Technology
3rd Author's Name Susumu Horiguchi
3rd Author's Affiliation School of Information Science Japan Advanced Institute of Science and Technology
Date 1998/12/10
Paper # VLD98-99,CPSY98-119
Volume (vol) vol.98
Number (no) 446
Page pp.pp.-
#Pages 8
Date of Issue