| Presentation | 1998/12/11 A Clock ON/OFF Scheduling for Low Power Multi-Processor Design Toshihiko YOKOMARU, Atsushi TAKAHASHI, Yoji KAJITANI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | On a clock-driven system with multiple processors, we consider the model that the set of processors is clustered into blocks and timing of clock-supply is controlled at block level. By the assumption that the power is mainly consumed by processors when they are supplied with clocks, we formulate a job scheduling problem to make the power consumption of the system small. We propose an easily implementable heuristic algorithm BF-ASAP(Best-Fit/As Soon As Possible)which optimizes each job sequentially in each block. We show about 30% power reduction on randomly generated instances in which 100 processors are clustered into 10 blocks, to show the method being promising. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Low Power / Job Scheduling / NP-complete / Best-Fit / ASAP |
| Paper # | VLD98-128,CPSY98-148 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1998/12/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Clock ON/OFF Scheduling for Low Power Multi-Processor Design |
| Sub Title (in English) | |
| Keyword(1) | Low Power |
| Keyword(2) | Job Scheduling |
| Keyword(3) | NP-complete |
| Keyword(4) | Best-Fit |
| Keyword(5) | ASAP |
| 1st Author's Name | Toshihiko YOKOMARU |
| 1st Author's Affiliation | Dept. of Electrical and Electronic Engrg., Tokyo Inst. of Tech.() |
| 2nd Author's Name | Atsushi TAKAHASHI |
| 2nd Author's Affiliation | Dept. of Electrical and Electronic Engrg., Tokyo Inst. of Tech. |
| 3rd Author's Name | Yoji KAJITANI |
| 3rd Author's Affiliation | Dept. of Electrical and Electronic Engrg., Tokyo Inst.of Tech. |
| Date | 1998/12/11 |
| Paper # | VLD98-128,CPSY98-148 |
| Volume (vol) | vol.98 |
| Number (no) | 447 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |