| Presentation | 1998/12/11 An ASIC Design Methodology Using an Integrated Design Tool for FPGAs K Kobayashi, H Kanbara, H Onodera, K Tamaru, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Here, we compare ASIC design methodologies between MAX+PLUSII for FPGAs and conventional ASIC design environment by Verilog-HDL or VHDL. MAX+PLUSII is an FPGA design framework that integrates a schematic entry, an HDL Compiler and a simulator. If MAX can be applied to ASIC designs, designers can easily master the design flow owing to its user-friendly GUI environment. We apply the proposed MAX+PLUSII-based ASIC design methodology to two designs, "a BCD calculator", and "A Microprocessor for Education of Computer Hardware and LSI Design: Kuechip2". The proposed method achieves good performance and small area. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Altera / MAX+PLUSII / Integrated Design Tool / ASIC |
| Paper # | VLD98-118,CPSY98-138 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1998/12/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An ASIC Design Methodology Using an Integrated Design Tool for FPGAs |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Altera |
| Keyword(3) | MAX+PLUSII |
| Keyword(4) | Integrated Design Tool |
| Keyword(5) | ASIC |
| 1st Author's Name | K Kobayashi |
| 1st Author's Affiliation | Graduate School of Informatics, Kyoto University() |
| 2nd Author's Name | H Kanbara |
| 2nd Author's Affiliation | Graduate School of Informatics, Kyoto University:Advanced Software Technology & Mechatronics Research Institute of KYOTO |
| 3rd Author's Name | H Onodera |
| 3rd Author's Affiliation | Graduate School of Informatics, Kyoto University |
| 4th Author's Name | K Tamaru |
| 4th Author's Affiliation | Graduate School of Informatics, Kyoto University |
| Date | 1998/12/11 |
| Paper # | VLD98-118,CPSY98-138 |
| Volume (vol) | vol.98 |
| Number (no) | 447 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |