Presentation 1995/10/20
Design and Implementation of Reconfigrable General Purpose Coprocessor GPCP-SS
Yasufumi Itoh, Makoto Hirao, Shinji Kimura, Katsumasa Watanabe,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) we have proposed General Purpose Coprocessor (GPCP), which is a reconfigurable hardware attached t6 a bus in a computer system. In the paper, we describe about the design and implementation of GPCP-SS for connecting SBus in SPARCstations. GPCP-SS is constructed from 4 FPGA's for implementing reconfigurable hardware, 1 mega bytes of cache memory, a SBus controller and a configuration controller of FPGA's. GPCP-SS can access resources in computer system, such as main memory, video RAM, etc. We show the evaluation of GPCP-SS with some simple processing.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Hardware/Software Codesign / Hardware/Software Cooperation / FPGA
Paper # VLD95-100,FTS95-62
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Committee VLD
Conference Date 1995/10/20(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design and Implementation of Reconfigrable General Purpose Coprocessor GPCP-SS
Sub Title (in English)
Keyword(1) Hardware/Software Codesign
Keyword(2) Hardware/Software Cooperation
Keyword(3) FPGA
1st Author's Name Yasufumi Itoh
1st Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology()
2nd Author's Name Makoto Hirao
2nd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology
3rd Author's Name Shinji Kimura
3rd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology
4th Author's Name Katsumasa Watanabe
4th Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology
Date 1995/10/20
Paper # VLD95-100,FTS95-62
Volume (vol) vol.95
Number (no) 307
Page pp.pp.-
#Pages 8
Date of Issue