| Presentation | 1995/10/20 A Data Path Scheduling Algorithm with Resource Allocation for DSP Synthesis Koichi NISHIDA, Nozomu TOGAWA, Masao SATO, Tatsuo OHTSUKI, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In high-level synthesis for DSP data paths, scheduling of data flow graphs plays a primary role. In scheduling, it is required that a hardware resource amount is estimated as precisely as possible, and that operations are assigned to control steps so that a resource amount is minimized. In addition, pipelining that overlaps operations is necessary in high-speed DSP application such as image processing. In this paper, we propose a time constraint scheduling algorithm that deals with pipelining, and minimizes both functional unit and register costs. In our algorithm, the control step regarded as the worst in terms of a resource cost is gradually eliminated for each operation in each iteration. Finally, each operation is assigned to one control step. Experimental results for practical DSP data flow graphs show that our algorithm obtains near optimal solutions in less than one second. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DSP / high-level synthesis / scheduling / resource allocation / pipelining |
| Paper # | VLD95-97,FTS95-59 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
|---|---|
| Conference Date | 1995/10/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Data Path Scheduling Algorithm with Resource Allocation for DSP Synthesis |
| Sub Title (in English) | |
| Keyword(1) | DSP |
| Keyword(2) | high-level synthesis |
| Keyword(3) | scheduling |
| Keyword(4) | resource allocation |
| Keyword(5) | pipelining |
| 1st Author's Name | Koichi NISHIDA |
| 1st Author's Affiliation | Dept. of Electronics and Communication Engineering Waseda University() |
| 2nd Author's Name | Nozomu TOGAWA |
| 2nd Author's Affiliation | Dept. of Electronics and Communication Engineering Waseda University |
| 3rd Author's Name | Masao SATO |
| 3rd Author's Affiliation | Dept. of Electronics and Communication Engineering Waseda University |
| 4th Author's Name | Tatsuo OHTSUKI |
| 4th Author's Affiliation | Dept. of Electronics and Communication Engineering Waseda University |
| Date | 1995/10/20 |
| Paper # | VLD95-97,FTS95-59 |
| Volume (vol) | vol.95 |
| Number (no) | 307 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |