Presentation 1995/10/20
An Algorithm for Generating Data Flow Graphs from Behavioral Descriptions
Yoko KAWATA, Nozomu TOGAWA, Masao SATO, Tatsuo OHTSUKI,
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Abstract(in English) In this paper, we propose an algorithm for generating data flow graphs (DFGs) from a behavioral description which consists of algebraic expressions without control structures. DFG generation is the first task of the high level synthesis for designing DSP. Since the results of the synthesis much depend on a DFG structure, it is important to consider design requirements such as time and area during generating DFGs. In the proposed technique, we transform a DFG structure and make operations in parallel without increasing a resource cost so that the DFG can satisfy a given time constraint. Among generated DFGs satisfying a given time constraint, multiple DFGs are chosen based on the estimated resource costs. We can obtain better results by preparing multiple DFGs and synthesizing each of them. Experimental results show that we obtain multiple DFGs with low resource costs from a practical behavioral description.
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Keyword(in English) high level synthesis / DSP / data flow graph / transformation
Paper # VLD95-96,FTS95-58
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Committee VLD
Conference Date 1995/10/20(1days)
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Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Algorithm for Generating Data Flow Graphs from Behavioral Descriptions
Sub Title (in English)
Keyword(1) high level synthesis
Keyword(2) DSP
Keyword(3) data flow graph
Keyword(4) transformation
1st Author's Name Yoko KAWATA
1st Author's Affiliation Dept. of Electronics and Communication Engineering Waseda University()
2nd Author's Name Nozomu TOGAWA
2nd Author's Affiliation Dept. of Electronics and Communication Engineering Waseda University
3rd Author's Name Masao SATO
3rd Author's Affiliation Dept. of Electronics and Communication Engineering Waseda University
4th Author's Name Tatsuo OHTSUKI
4th Author's Affiliation Dept. of Electronics and Communication Engineering Waseda University
Date 1995/10/20
Paper # VLD95-96,FTS95-58
Volume (vol) vol.95
Number (no) 307
Page pp.pp.-
#Pages 8
Date of Issue