Presentation 1995/10/20
Power Reduction Method by Logic Optimization Techniques
Hiroaki Ueda, Kozo Kinoshita,
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Abstract(in English) This paper presents a power reduction method which reduces the average power dissipation using transduction method. The method transforms the circuit into a circuit whose power dissipation is lower than that of original, even if the number of literals or transistors may be increased due to the transformation. Thus, it is expected that power reduction capability of this method is very high. Next, we apply the power reduction method for large circuits by sub-circuit extraction. Two extraction methods are described. The one is fanout-oriented extraction and the other is distance-oriented extraction that . For both methods, experimental results for benchmark circuits are also reported.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Logic Optimization / Transduction Method / power Dissipation / Transition Probability / Sub-circuit Extraction
Paper # VLD95-95,FTS95-57
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Committee VLD
Conference Date 1995/10/20(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Power Reduction Method by Logic Optimization Techniques
Sub Title (in English)
Keyword(1) Logic Optimization
Keyword(2) Transduction Method
Keyword(3) power Dissipation
Keyword(4) Transition Probability
Keyword(5) Sub-circuit Extraction
1st Author's Name Hiroaki Ueda
1st Author's Affiliation Dept. of Intelligent Systems, Faculty of Information sciences, Hiroshima City University()
2nd Author's Name Kozo Kinoshita
2nd Author's Affiliation Dept. of Applied Physics, Faculty of Engineering, Osaka University
Date 1995/10/20
Paper # VLD95-95,FTS95-57
Volume (vol) vol.95
Number (no) 307
Page pp.pp.-
#Pages 7
Date of Issue