| Presentation | 1995/10/20 Optimization of Sequential Circuits using Retiming and Redundancy Removal Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The existence of sequential redundancy in logic circuits will have bad effects on chip size and testability of sequential circuits. In this paper we propose a redundancy removal method for reducing the number of gates and flip-flops. The proposed method is comprised of redundancy removal using a combinational test generator and retiming. Retiming is utilized for two purposes: One is for finding sequential redundancies and another is for reducing the number of flip-flops. Applying redundancy removal techniques after retiming, not only all combinational redundancies but also several sequential redundancies can be removed. Experimental results for ISCAS'89 benchmark circuits show that this method can remove many sequential redundancies and reduce the number of gates and flip-flops. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Sequential logic optimization / retiming / fault detection / redundancy removal / stuck-at faults |
| Paper # | VLD95-94,FTS95-56 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1995/10/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Optimization of Sequential Circuits using Retiming and Redundancy Removal |
| Sub Title (in English) | |
| Keyword(1) | Sequential logic optimization |
| Keyword(2) | retiming |
| Keyword(3) | fault detection |
| Keyword(4) | redundancy removal |
| Keyword(5) | stuck-at faults |
| 1st Author's Name | Hiroyuki Yotsuyanagi |
| 1st Author's Affiliation | Department of Applied Physics, Faculty of Engineering, Osaka University() |
| 2nd Author's Name | Seiji Kajihara |
| 2nd Author's Affiliation | Department of Applied Physics, Faculty of Engineering, Osaka University |
| 3rd Author's Name | Kozo Kinoshita |
| 3rd Author's Affiliation | Department of Applied Physics, Faculty of Engineering, Osaka University |
| Date | 1995/10/20 |
| Paper # | VLD95-94,FTS95-56 |
| Volume (vol) | vol.95 |
| Number (no) | 307 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |