Presentation 1995/10/20
On the Synthesis of Synchronizable Finite State Machines with Partial Scan
Hiroshi YOURA, Tomoo INOUE, Toshimitsu MASUZAWA, Hideo FUJIWARA,
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Abstract(in English) In this paper, we present an approach to synthesizing synchronizable finite state machines using partial scan. We propose an extended synchronizing sequence which consists of normal input-patterns and partial-scan input-patterns. We consider two problems of extended synchronization; to obtain the minimum number of scannable state-valiables to synchronize an FSM, and to obtain the minimum length of extended synchronizing sequence and its state assignment for an FSM, given the number of scannable state-valiables.
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Keyword(in English) Testability / FSM / Synchronizing sequence / Partial Scan / Extended Synchronization
Paper # VLD95-93,FTS95-55
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Committee VLD
Conference Date 1995/10/20(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) On the Synthesis of Synchronizable Finite State Machines with Partial Scan
Sub Title (in English)
Keyword(1) Testability
Keyword(2) FSM
Keyword(3) Synchronizing sequence
Keyword(4) Partial Scan
Keyword(5) Extended Synchronization
1st Author's Name Hiroshi YOURA
1st Author's Affiliation Graduate School of Information Science Nara Institute of Science and Technology()
2nd Author's Name Tomoo INOUE
2nd Author's Affiliation Graduate School of Information Science Nara Institute of Science and Technology
3rd Author's Name Toshimitsu MASUZAWA
3rd Author's Affiliation Graduate School of Information Science Nara Institute of Science and Technology
4th Author's Name Hideo FUJIWARA
4th Author's Affiliation Graduate School of Information Science Nara Institute of Science and Technology
Date 1995/10/20
Paper # VLD95-93,FTS95-55
Volume (vol) vol.95
Number (no) 307
Page pp.pp.-
#Pages 8
Date of Issue