Presentation 1995/10/20
On Invariant Implication Relations in Redundancy Removal for Combinational Circuits
Seiji Kajihara, Hideyuki Ichihara, Kozo Kinoshita,
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Abstract(in English) In redundancy removal for combinational circuits using SOCRATES based test generation, it was required to do over static learning again whenever a redundant fault is removed because implication relations of the original circuits may change. In this paper we discuss invariance of implication relations derived by static learning in modifying circuits by redundancy removal, then propose an efficient redundancy removal method in which invariant implication relations are used for redundancy identification in spite of doing over static learning. Experimental results for benchmark circuits show that the proposed method is up to 60 times faster than the previous method.
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Keyword(in English) redundancy removal / test generation / logic synthesis / static learning / combinational circuit
Paper # VLD95-92,FTS95-54
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Committee VLD
Conference Date 1995/10/20(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) On Invariant Implication Relations in Redundancy Removal for Combinational Circuits
Sub Title (in English)
Keyword(1) redundancy removal
Keyword(2) test generation
Keyword(3) logic synthesis
Keyword(4) static learning
Keyword(5) combinational circuit
1st Author's Name Seiji Kajihara
1st Author's Affiliation Dept. of Applied Physics, Osaka University()
2nd Author's Name Hideyuki Ichihara
2nd Author's Affiliation Dept. of Applied Physics, Osaka University
3rd Author's Name Kozo Kinoshita
3rd Author's Affiliation Dept. of Applied Physics, Osaka University
Date 1995/10/20
Paper # VLD95-92,FTS95-54
Volume (vol) vol.95
Number (no) 307
Page pp.pp.-
#Pages 7
Date of Issue