Presentation | 1995/10/19 Power-Optimal Transistor Sizing Incorporating Short-Circuit Effect Naohito Kojima, Masaaki Yamada, Takashi Mitsuhashi, Nobuyuki Goto, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | A new transistor sizing method which optimizes the current dissipation of logic circuits is proposed in this paper. Experimental results show that this new method reduces the total current dissipation along a path about 5% further than the previous sizing methods by considering the temporary short circuit in switching. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | transistor sizing / short-circuit / current dissipation / posynomial / convex programming |
Paper # | VLD95-88,FTS95-50 |
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Conference Information | |
Committee | VLD |
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Conference Date | 1995/10/19(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Power-Optimal Transistor Sizing Incorporating Short-Circuit Effect |
Sub Title (in English) | |
Keyword(1) | transistor sizing |
Keyword(2) | short-circuit |
Keyword(3) | current dissipation |
Keyword(4) | posynomial |
Keyword(5) | convex programming |
1st Author's Name | Naohito Kojima |
1st Author's Affiliation | Semiconductor DA & Test Engineering Center, Toshiba Corporation() |
2nd Author's Name | Masaaki Yamada |
2nd Author's Affiliation | Semiconductor DA & Test Engineering Center, Toshiba Corporation |
3rd Author's Name | Takashi Mitsuhashi |
3rd Author's Affiliation | Semiconductor DA & Test Engineering Center, Toshiba Corporation |
4th Author's Name | Nobuyuki Goto |
4th Author's Affiliation | R&D Center, Toshiba Corporation |
Date | 1995/10/19 |
Paper # | VLD95-88,FTS95-50 |
Volume (vol) | vol.95 |
Number (no) | 306 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |