| Presentation | 1995/10/19 A Timing Driven Placement Algorithm in Arithmetic Logic Circuits Takeshi Nakamura, Akimichi Kojima, Katsuya Furuki, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a placement algorithm mainly dedicated to datapath elements and minimized a difference of delay time between bits. This algorithm decides a relative placement by tracing functional blocks in logic circuits based on the data signal path utilizing bit width and depth of logic stages. The placement using this algorithm shows that a difference of wire length in every logic stage is smaller than current auto placement and that this method is effective. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | LSI CAD / Arithmetic / Logic Circuits / Placement / Layout |
| Paper # | VLD95-86,FTS95-48 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1995/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Timing Driven Placement Algorithm in Arithmetic Logic Circuits |
| Sub Title (in English) | |
| Keyword(1) | LSI CAD |
| Keyword(2) | Arithmetic |
| Keyword(3) | Logic Circuits |
| Keyword(4) | Placement |
| Keyword(5) | Layout |
| 1st Author's Name | Takeshi Nakamura |
| 1st Author's Affiliation | NEC Corporation() |
| 2nd Author's Name | Akimichi Kojima |
| 2nd Author's Affiliation | NEC Corporation |
| 3rd Author's Name | Katsuya Furuki |
| 3rd Author's Affiliation | NEC Corporation |
| Date | 1995/10/19 |
| Paper # | VLD95-86,FTS95-48 |
| Volume (vol) | vol.95 |
| Number (no) | 306 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |