Presentation	1995/10/19 On Functional Implication and Its Application to Equivalence Checking of Combinational Circuits Yusuke Matsunaga,
PDF Download Page	PDF download Page Link
Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	This paper describes a novel equivalence checking method of combinational circuits, which utilizes relations among internal signals represented by binary decision diagrams. To verify circuits efficiently, proper set of internal signals that are independent with each other should be chosen. A heuristic based on analysis of circuit structure is proposed to select such a set of internal signals. Experimental results using ISCAS'85 benchmarks demonstrate how the proposed method is effective. It proves equivalence of two circuits with 3000 gates in 20 seconds on SUN-4/10.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	equivalence checking / binary decision diagrams / implication
Paper #	VLD95-85,FTS95-47
Date of Issue

Conference Information
Committee	VLD
Conference Date	1995/10/19(1days)
Place (in Japanese)	(See Japanese page)
Place (in English)
Topics (in Japanese)	(See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To	VLSI Design Technologies (VLD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	On Functional Implication and Its Application to Equivalence Checking of Combinational Circuits
Sub Title (in English)
Keyword(1)	equivalence checking
Keyword(2)	binary decision diagrams
Keyword(3)	implication
1st Author's Name	Yusuke Matsunaga
1st Author's Affiliation	Fujitsu Laboratories LTD.()
Date	1995/10/19
Paper #	VLD95-85,FTS95-47
Volume (vol)	vol.95
Number (no)	306
Page	pp.pp.-
#Pages	8
Date of Issue