Presentation | 1995/10/19 Logic Verification for Super Scalar MPU Takeshi Ibusuki, Hideki Adachi, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper provides the logic simulation methodology adopted on HaL processor design verification. The effectiveness of random verification program and application programs are well known as a good verification tool for the logic simulation. We developed some random verification programs which are well focused on hardware behavior. It, however, takes billions of machine cycles to run those programs until the design fix. In order to solve the problem, we embedded the efficient method, signature-compare and assertion-check,into our logic simulation environment. With the unique ideas, we ran a variety of programs in limited period, and fulfilled our goal. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Processors / Logic Simulation / Logic Verification / Random programs / Signature / Assertion |
Paper # | VLD95-83,FTS95-45 |
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Conference Information | |
Committee | VLD |
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Conference Date | 1995/10/19(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Logic Verification for Super Scalar MPU |
Sub Title (in English) | |
Keyword(1) | Processors |
Keyword(2) | Logic Simulation |
Keyword(3) | Logic Verification |
Keyword(4) | Random programs |
Keyword(5) | Signature |
Keyword(6) | Assertion |
1st Author's Name | Takeshi Ibusuki |
1st Author's Affiliation | 2TMP DEPT. Fujitsu LTD.() |
2nd Author's Name | Hideki Adachi |
2nd Author's Affiliation | Babu Turumella HAL Computer Systems |
Date | 1995/10/19 |
Paper # | VLD95-83,FTS95-45 |
Volume (vol) | vol.95 |
Number (no) | 306 |
Page | pp.pp.- |
#Pages | 8 |
Date of Issue |