Presentation 1995/10/19
A Fault Location System for Complex LSIs
Masaki Gotoh, Hiroshi Odani, Fumihiko Shirotori,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We will present a fault locator that is built almost entirely by software tools. The system speed has increased tenfold compared to its predecessor even though the complexity of the LSI being analyzed has, at minimum, quadrupled. The system can locate a single fault from a 250K gate circuit in a matter of minutes. The fault can then be viewed in a schematic or layout diagram. Furthermore, particles detected from the particle inspection unit can be viewed with the layout diagram to find correlations between these particles and the fault locator results.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Fault Analysis / Fault Location / Fault Simulation / Direct Scan Fault Simulation / Delay Fault
Paper # VLD95-82,FTS95-44
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Conference Information
Committee VLD
Conference Date 1995/10/19(1days)
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Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Fault Location System for Complex LSIs
Sub Title (in English)
Keyword(1) Fault Analysis
Keyword(2) Fault Location
Keyword(3) Fault Simulation
Keyword(4) Direct Scan Fault Simulation
Keyword(5) Delay Fault
1st Author's Name Masaki Gotoh
1st Author's Affiliation Device Development Center, Hitachi Ltd. Design Automation Development Department, DA4 Group()
2nd Author's Name Hiroshi Odani
2nd Author's Affiliation Device Development Center, Hitachi Ltd. Design Automation Development Department, DA4 Group
3rd Author's Name Fumihiko Shirotori
3rd Author's Affiliation Device Development Center, Hitachi Ltd. Design Automation Development Department, DA4 Group
Date 1995/10/19
Paper # VLD95-82,FTS95-44
Volume (vol) vol.95
Number (no) 306
Page pp.pp.-
#Pages 5
Date of Issue