| Presentation | 1995/10/19 On Testing of Josephson Logic Circuits Teruhiko Yamada, Tsuyoshi Sasaki, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We analyzed the electric manifestation of the 4JL(four Josephson junction logic)gates with a defect by computer simulation, and proved that: (1) Logic testing can detect less than half of the defects which are due to process instabilities and contaminations during the fabrication processes. (2) A high defect coverage is achievable by monitoring current drawn from power suppliers. (3) Current testing may be very effective for the testing of Josephson logic circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Josephson logic circuit / logic testing / current testing / defect / fault |
| Paper # | VLD95-81,FTS95-43 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1995/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On Testing of Josephson Logic Circuits |
| Sub Title (in English) | |
| Keyword(1) | Josephson logic circuit |
| Keyword(2) | logic testing |
| Keyword(3) | current testing |
| Keyword(4) | defect |
| Keyword(5) | fault |
| 1st Author's Name | Teruhiko Yamada |
| 1st Author's Affiliation | Dept. of Computer Science, Meiji University() |
| 2nd Author's Name | Tsuyoshi Sasaki |
| 2nd Author's Affiliation | Dept. of Computer Science, Meiji University |
| Date | 1995/10/19 |
| Paper # | VLD95-81,FTS95-43 |
| Volume (vol) | vol.95 |
| Number (no) | 306 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |