| Presentation | 1995/10/19 On Improvement of an ATPG based on Real-valued Logic Simulation Tsuyoshi Shinogi, Tomoyuki Uchida, Hidehiko Kita, Terumine Hayashi, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An ATPG based on real-valued logic simulation has already been proposed. We enhance its basic performance by introducing the following techniques to the combinational ATPG. For speeding up, (1) eliminating the computation for real-valued logic simulation of ineffective gates for detection of each fault and also (2) eliminating the computation for gates unreachable from the selected primary input in real-valued logic simulation. And for improving fault coverage, (3) the iterative improvement procedure by multiple random input patterns and (4) adjustment of the output real value of each gate. As a result, by the ATPG based on real-valued logic simulation, we have achieved l00% fault coverage for all the faults without redundant faults in each ISCAS '85 and ISCAS '89 (assuming full-scan) circuit in practical time. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | automatic test pattern generation / real-valued logic simulation / iterative improvement method / fault detection |
| Paper # | VLD95-79,FTS95-41 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
|---|---|
| Conference Date | 1995/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On Improvement of an ATPG based on Real-valued Logic Simulation |
| Sub Title (in English) | |
| Keyword(1) | automatic test pattern generation |
| Keyword(2) | real-valued logic simulation |
| Keyword(3) | iterative improvement method |
| Keyword(4) | fault detection |
| 1st Author's Name | Tsuyoshi Shinogi |
| 1st Author's Affiliation | Mie University() |
| 2nd Author's Name | Tomoyuki Uchida |
| 2nd Author's Affiliation | Mie University |
| 3rd Author's Name | Hidehiko Kita |
| 3rd Author's Affiliation | Mie University |
| 4th Author's Name | Terumine Hayashi |
| 4th Author's Affiliation | Mie University |
| Date | 1995/10/19 |
| Paper # | VLD95-79,FTS95-41 |
| Volume (vol) | vol.95 |
| Number (no) | 306 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |