Presentation	1996/3/8 Fanout-tree Restructuring Algorithm for Post-placement Timing Optimization T. Aoki, M. Murakata, T. Mituhashi, N. Goto,
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Abstract(in English)	This paper proposes a fanout-tree restructuring algorithm for post-placement timing optimization to meet timing constraints. The proposed algorithm restructures a fanout-tree by finding a tree in a graph which represents a multi-terminal net, and inserts buffer cells and resizes cells based on an accurate interconnection RC delay without degrading routability. The algorithm has been implemented and applied to a number of layout data generated by timing driven placement. Application results show a 17% reduction in circuit delay on the average.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	fanout problem / RC delay / timing driven
Paper #	VLD95-153,ICD95-253
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Conference Information
Committee	VLD
Conference Date	1996/3/8(1days)
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Paper Information
Registration To	VLSI Design Technologies (VLD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Fanout-tree Restructuring Algorithm for Post-placement Timing Optimization
Sub Title (in English)
Keyword(1)	fanout problem
Keyword(2)	RC delay
Keyword(3)	timing driven
1st Author's Name	T. Aoki
1st Author's Affiliation	Semiconductor DA & Test Engineering Center, TOSHIBA()
2nd Author's Name	M. Murakata
2nd Author's Affiliation	Semiconductor DA & Test Engineering Center, TOSHIBA
3rd Author's Name	T. Mituhashi
3rd Author's Affiliation	Semiconductor DA & Test Engineering Center, TOSHIBA
4th Author's Name	N. Goto
4th Author's Affiliation	Research and Development Center, TOSHIBA
Date	1996/3/8
Paper #	VLD95-153,ICD95-253
Volume (vol)	vol.95
Number (no)	562
Page	pp.pp.-
#Pages	8
Date of Issue