| Presentation | 1996/3/8 A synthesis method of fault-tolerant system for a singular operational module fault Tsuyoshi Yaguchi, Mineo Kaneko, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The high-level synthesis for generating fault-torelant systems of signal processing has been discussed. In this paper, a new synthesis method for redundanced Data Flow Graph with alogorithm-level fault tolerance and mapping them to hardware-time domain are proposed. The determination of error correcting points, the grouping of error correcting points are key to the optimality, but still open. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Fault tolerant / High-level synthesis / DFG / WCC method |
| Paper # | VLD95-144,ICD95-244 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1996/3/8(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A synthesis method of fault-tolerant system for a singular operational module fault |
| Sub Title (in English) | |
| Keyword(1) | Fault tolerant |
| Keyword(2) | High-level synthesis |
| Keyword(3) | DFG |
| Keyword(4) | WCC method |
| 1st Author's Name | Tsuyoshi Yaguchi |
| 1st Author's Affiliation | Department of Electorical and Electronic Engineering, Tokyo Institute of Technology() |
| 2nd Author's Name | Mineo Kaneko |
| 2nd Author's Affiliation | Department of Electorical and Electronic Engineering, Tokyo Institute of Technology |
| Date | 1996/3/8 |
| Paper # | VLD95-144,ICD95-244 |
| Volume (vol) | vol.95 |
| Number (no) | 562 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |