| Presentation | 1996/3/7 High-Level Synthesis for Array Architecture Digital Signal Processing Systems Tadashi Iwata, Kazuhito Ito, Hiroaki Kunieda, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In high-level synthesis for digital signal processing systems of array structured architecture, the most important procedure is scheduling by taking into account the allocation of operations to processors and the communication time between processors. In this paper we propose a scheduling method which derives an optimal schedule of a given signal processing algorithm achieving the minimum iteration period and latency for a specified processor array by using integer linear programming. Furthermore, we improve the scheduling method so that it can be applied to large scale signal processing algorithms without degrading the schedule optimality. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | high-level synthesis / processer array / scheduling / integer linear programming |
| Paper # | VLD95-138,ICD95-238 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1996/3/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-Level Synthesis for Array Architecture Digital Signal Processing Systems |
| Sub Title (in English) | |
| Keyword(1) | high-level synthesis |
| Keyword(2) | processer array |
| Keyword(3) | scheduling |
| Keyword(4) | integer linear programming |
| 1st Author's Name | Tadashi Iwata |
| 1st Author's Affiliation | Dept. of Elec. and Elect. Eng. Tokyo Institute of Technology() |
| 2nd Author's Name | Kazuhito Ito |
| 2nd Author's Affiliation | Dept. of Elec. and Elect. Syst. Eng. Saitama University |
| 3rd Author's Name | Hiroaki Kunieda |
| 3rd Author's Affiliation | Dept. of Elec. and Elect. Eng. Tokyo Institute of Technology |
| Date | 1996/3/7 |
| Paper # | VLD95-138,ICD95-238 |
| Volume (vol) | vol.95 |
| Number (no) | 561 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |