Presentation 1995/12/14
A Global Code Scheduling Technique with Register Allocation for Fine Grain Parallel Processors
Akihiko Inoue, Hiroki Akaboshi, Hiroyuki Tomiyama, Kazutoshi Wakabayashi, Hiroto Yasuura,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We propose a scheduling algorithm which performs global code scheduling and register allocation simultaneously. In most of previous register allocation techniques, instruction level parallelism is not considered. So it is difficult to bring out the maximum performance of processors. Scheduling instructions simultaneously with register allocation, we have the advantages; 1) In the scheduling process, there are no constraints by extra data dependences which the register allocator produces. 2) Spill codes inserted by the register allocator itself can be also scheduled simultaneously. We have evaluated our scheduling algorithm using several benchmark programs.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Condition Vector / Global Code Scheduling / Instruction Level Parallelism / Register Allocation / Compiler
Paper # VLD95-104
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Committee VLD
Conference Date 1995/12/14(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Global Code Scheduling Technique with Register Allocation for Fine Grain Parallel Processors
Sub Title (in English)
Keyword(1) Condition Vector
Keyword(2) Global Code Scheduling
Keyword(3) Instruction Level Parallelism
Keyword(4) Register Allocation
Keyword(5) Compiler
1st Author's Name Akihiko Inoue
1st Author's Affiliation Interdisciplinary Graduate School of Engineering Sciences, Kyushu University()
2nd Author's Name Hiroki Akaboshi
2nd Author's Affiliation Interdisciplinary Graduate School of Engineering Sciences, Kyushu University
3rd Author's Name Hiroyuki Tomiyama
3rd Author's Affiliation Interdisciplinary Graduate School of Engineering Sciences, Kyushu University
4th Author's Name Kazutoshi Wakabayashi
4th Author's Affiliation C&C Research Laboratory, NEC Corporation
5th Author's Name Hiroto Yasuura
5th Author's Affiliation Interdisciplinary Graduate School of Engineering Sciences, Kyushu University
Date 1995/12/14
Paper # VLD95-104
Volume (vol) vol.95
Number (no) 420
Page pp.pp.-
#Pages 6
Date of Issue