Presentation	1995/12/14 A Scheduling Method for Pipelined Datapaths Considering Register-to-Register Data Transfers Katsumi HARASHIMA, Hironori KOMI, Kunio FUKUNAGA,
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Abstract(in English)	In high level synthesis, scheduling is an important stage which assigns each operation appeared in a data flow graph to a specific control step, of which results influence the design quality directly. This paper describes a scheduling approach for pipelined datapaths. Since no previous approach estimates the interconnection cost between registers (register-to-register cost), our approach introduces a datapath model with the interconnection between registers across buses, and minimizes the total hardware cost including the register-to-register cost with Integer Linear Programming approaches. Consequently the proposed approach can estimate the hardware cost exactly in the scheduling phase.
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Paper #	VLD95-102
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Committee	VLD
Conference Date	1995/12/14(1days)
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Registration To	VLSI Design Technologies (VLD)
Language	JPN
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Title (in English)	A Scheduling Method for Pipelined Datapaths Considering Register-to-Register Data Transfers
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1st Author's Name	Katsumi HARASHIMA
1st Author's Affiliation	Faculty of Engineering, University of Osaka Prefecture()
2nd Author's Name	Hironori KOMI
2nd Author's Affiliation	Hitachi Ltd.
3rd Author's Name	Kunio FUKUNAGA
3rd Author's Affiliation	Faculty of Engineering, University of Osaka Prefecture
Date	1995/12/14
Paper #	VLD95-102
Volume (vol)	vol.95
Number (no)	420
Page	pp.pp.-
#Pages	6
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