Presentation 1995/9/13
Design of Pseudo Asynchronous Microprocessor Using Synchronous Completion Detection Adder
Makoto Ikeda, JiHan Lee, Kunihiro Asada,
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Abstract(in English) We describe Split Ripple Carry Adder (SRCA), which detects completion signal synchronously, to enhance mean operation time with small hardware costs. To use SRCA in microprocessors, we studied pseudo asynchronous microprocessor, which uses automaton with variable delay to control block synchronization free from clock skew. We demonstrate that the effectiveness of the pseudo asynchronous microprocessor is about 74% using SRCA with variable delay and load store unit with longer delay.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Pseudo asynchronous / synchronous completion detection / microprocessor / automaton
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Committee VLD
Conference Date 1995/9/13(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Design of Pseudo Asynchronous Microprocessor Using Synchronous Completion Detection Adder
Sub Title (in English)
Keyword(1) Pseudo asynchronous
Keyword(2) synchronous completion detection
Keyword(3) microprocessor
Keyword(4) automaton
1st Author's Name Makoto Ikeda
1st Author's Affiliation Affiliation: Faculty of Engineering, University of Tokyo()
2nd Author's Name JiHan Lee
2nd Author's Affiliation Affiliation: Faculty of Engineering, University of Tokyo
3rd Author's Name Kunihiro Asada
3rd Author's Affiliation Affiliation: Faculty of Engineering, University of Tokyo
Date 1995/9/13
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Volume (vol) vol.95
Number (no) 230
Page pp.pp.-
#Pages 6
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