Presentation | 1993/12/17 Datapath optimization methodlogy in PEAS-I:a hardware/software codesign system for ASIP Yoshimichi Honma, Akichika Shiomi, Masaharu Imai, Nobuyuki Hikichi, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In this paper,we present the hardware generation method in PEAS- I,which is a hardware, software codesign system for ASIP development.PEAS-I system analyzes a set of application programs and associated data set and determines optimal instruction set. Hardware generator accepts the determined instruction set and then generates CPU core design in the form of an HDL.The experimental results give the information to optimize the ASIP architecture taking the trade-off of coniputatiolial module and register file into account. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | VLSI / ASIP / Hardware/oftware Codesign / High-level Synthesis |
Paper # | VLD93-94 |
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Committee | VLD |
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Conference Date | 1993/12/17(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Datapath optimization methodlogy in PEAS-I:a hardware/software codesign system for ASIP |
Sub Title (in English) | |
Keyword(1) | VLSI |
Keyword(2) | ASIP |
Keyword(3) | Hardware/oftware Codesign |
Keyword(4) | High-level Synthesis |
1st Author's Name | Yoshimichi Honma |
1st Author's Affiliation | Toyohashi University of Technology() |
2nd Author's Name | Akichika Shiomi |
2nd Author's Affiliation | Toyohashi University of Technology |
3rd Author's Name | Masaharu Imai |
3rd Author's Affiliation | Toyohashi University of Technology |
4th Author's Name | Nobuyuki Hikichi |
4th Author's Affiliation | SRA |
Date | 1993/12/17 |
Paper # | VLD93-94 |
Volume (vol) | vol.93 |
Number (no) | 392 |
Page | pp.pp.- |
#Pages | 8 |
Date of Issue |