Presentation 1993/12/17
Hardware generation methodology in PEAS-I:a hardware/software codesign system for ASIP
Takeharu Nakata, Jun Sato, Akichika Shiomi, Masaharu Imai, Nobuyuki Hikichi,
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Abstract(in English) In this paper,we present the hardware generation method in PEAS- I,which is a hardware, software codesign system for ASIP development.PEAS-I system analyzes a set of application programs and associated data set and determines optimal instruction set. Hardware generator accepts the determined instruction set and then generates CPU core design in the form of an HDL.The experimental results give the information to optimize the ASIP architecture taking the trade-off of coniputatiolial module and register file into account.
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Keyword(in English) VLSI / ASIP / Hardware/oftware Codesign / High-level synthesis / Hardware description language
Paper # VLD93-93
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Committee VLD
Conference Date 1993/12/17(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Hardware generation methodology in PEAS-I:a hardware/software codesign system for ASIP
Sub Title (in English)
Keyword(1) VLSI
Keyword(2) ASIP
Keyword(3) Hardware/oftware Codesign
Keyword(4) High-level synthesis
Keyword(5) Hardware description language
1st Author's Name Takeharu Nakata
1st Author's Affiliation Toyohashi University of Technology()
2nd Author's Name Jun Sato
2nd Author's Affiliation Tsuruoka National College of Technology
3rd Author's Name Akichika Shiomi
3rd Author's Affiliation Toyohashi University of Technology
4th Author's Name Masaharu Imai
4th Author's Affiliation Toyohashi University of Technology
5th Author's Name Nobuyuki Hikichi
5th Author's Affiliation SRA
Date 1993/12/17
Paper # VLD93-93
Volume (vol) vol.93
Number (no) 392
Page pp.pp.-
#Pages 8
Date of Issue