Presentation 1993/7/23
CEEDS-ASIC : ASIC Design and Debugging CAE System
Naoki Sano, Norio Kubo,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper presents a CAE systeia(CEEDS-ASIC),to effielitly assist ASIC design-and debugging.This system provides design and debugging enviroment in order to niake it possible to develop ASICs with high quality in a shorter design time.The systeju is intened for use to complement the HDL design lmethodology and consists of three major parts such as DA software packages,HDL libraries, modelsand engineerings.The effectiveness of this system has been already confirmed through actual chip developments such as a dedicated microprogrammable comuunication controller chip with 10Mbaud as an ASIC and a conmunication controller chip with 31.25Kbaud for standard Fieldbus based on IEC/ISA SP50 as an ASSP.
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Keyword(in English) HDL Desingn Methodology / Concurrent Design and Debugging Environment / System Level Simulation
Paper # VLD93-29
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Committee VLD
Conference Date 1993/7/23(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) CEEDS-ASIC : ASIC Design and Debugging CAE System
Sub Title (in English)
Keyword(1) HDL Desingn Methodology
Keyword(2) Concurrent Design and Debugging Environment
Keyword(3) System Level Simulation
1st Author's Name Naoki Sano
1st Author's Affiliation Devices Laboratory,Yokogawa Electric Corporation()
2nd Author's Name Norio Kubo
2nd Author's Affiliation Devices Laboratory,Yokogawa Electric Corporation
Date 1993/7/23
Paper # VLD93-29
Volume (vol) vol.93
Number (no) 162
Page pp.pp.-
#Pages 8
Date of Issue