| Presentation | 1998/3/6 Schedule-Clock-Tree Routing for Semi-Synchronous Circuits Kazunori INOUE, Wataru TAKAHASHI, Atsushi TAKAHASHI, Yoji KAJITANI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled.The algorithm to design an optimal clock-schedule was given.In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model.Following the deferred-merge-embedding(DME)framework, the algorithm generates a topology of the clock-tree and determines the locations and sizes of intermediate buffers simultaneously.The experimental results showed that this method constructs a clock-tree with moderate wire length for random layout of scheduled registers.Furthermore, the required wire length for gentle layout of scheduled registers was shown to be almost equal to that of zero-skew clock-trees. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | clock-tree / semi-synchronous circuit / schedule-clock-tree / zero-skew |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1998/3/6(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | VLSI Design Technologies (VLD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Schedule-Clock-Tree Routing for Semi-Synchronous Circuits |
| Sub Title (in English) | |
| Keyword(1) | clock-tree |
| Keyword(2) | semi-synchronous circuit |
| Keyword(3) | schedule-clock-tree |
| Keyword(4) | zero-skew |
| 1st Author's Name | Kazunori INOUE |
| 1st Author's Affiliation | Hitachi ULSI Engineering() |
| 2nd Author's Name | Wataru TAKAHASHI |
| 2nd Author's Affiliation | Dept.of Electrical and Electronic Engineering Tokyo Institute of Technology |
| 3rd Author's Name | Atsushi TAKAHASHI |
| 3rd Author's Affiliation | Dept.of Electrical and Electronic Engineering Tokyo Institute of Technology |
| 4th Author's Name | Yoji KAJITANI |
| 4th Author's Affiliation | Dept.of Electrical and Electronic Engineering Tokyo Institute of Technology |
| Date | 1998/3/6 |
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| Volume (vol) | vol.97 |
| Number (no) | 577 |
| Page | pp.pp.- |
| #Pages | 8 |
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