Presentation 1998/3/5
Reuse of Macro-cells and Performance Estimation
Kentaro SHIOMI, kei HIROSE, Hiroto YASUURA,
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Abstract(in English) As the size of devices shrinks into the deep submicron range, increase of design term and productivity crisis are emerged as new issues in system LSI design. These issues are mainly caused by difficulty in analysis and estimation of area, performance, and power consumption, in early stage of design of large system LSIs. Estimating the performance, power consumption and design cost acculately becomes more and more important.In this paper, we discuss on a reuse of floorplans and netlists of macro-cells for system LSI design to facilitate the performance estimation in early stage of design
Keyword(in Japanese) (See Japanese page)
Keyword(in English) System LSI / Reuse / Performance Estimation / Floorplanning / Macro-cell
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Committee VLD
Conference Date 1998/3/5(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Reuse of Macro-cells and Performance Estimation
Sub Title (in English)
Keyword(1) System LSI
Keyword(2) Reuse
Keyword(3) Performance Estimation
Keyword(4) Floorplanning
Keyword(5) Macro-cell
1st Author's Name Kentaro SHIOMI
1st Author's Affiliation Department of Computer Science and Communication Engineering Graduate School of Information Science and Electical Engineering()
2nd Author's Name kei HIROSE
2nd Author's Affiliation Department of Computer Science and Communication Engineering Graduate School of Information Science and Electical Engineering
3rd Author's Name Hiroto YASUURA
3rd Author's Affiliation Department of Computer Science and Communication Engneering Graduate School of Information Science and Electical Engineering
Date 1998/3/5
Paper #
Volume (vol) vol.97
Number (no) 576
Page pp.pp.-
#Pages 6
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