| Presentation | 1998/3/5 Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs Taku OHSAWA, Koji KAI, Kazuaki MURAKAMI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In merged DRAM/Iogic LSIs, it is nceessry to reduce the number of DRAM refrcshes because of higher heat dissipation caused by the logic portion on the same chip.In order to overcome this problem, we propose several DRAM refresh architectures.The basic idea behind them is to eliminate unnecessary DRAM refreshes.In addition we propose a method for reducing the number of DRAM refreshes by relocating data.In order to evaluate these architectures and method, we have estimated the DRAM refresh count in executing benchmark programs under several models which simulate each combination of them. As a result, in the most effective combination, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most of benchmark programs.In addition to it, we have taken normal DRAM access into account, even than we have obtained more then 50% reduction for several benchmarks. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DRAM / DRAM refresh / merged DRAM/logic / system LSI / low power |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1998/3/5(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs |
| Sub Title (in English) | |
| Keyword(1) | DRAM |
| Keyword(2) | DRAM refresh |
| Keyword(3) | merged DRAM/logic |
| Keyword(4) | system LSI |
| Keyword(5) | low power |
| 1st Author's Name | Taku OHSAWA |
| 1st Author's Affiliation | Department of Computer Science and Communication Engineering, Kyushu University() |
| 2nd Author's Name | Koji KAI |
| 2nd Author's Affiliation | Institute of Systems & Information Technologies/KYUSHU |
| 3rd Author's Name | Kazuaki MURAKAMI |
| 3rd Author's Affiliation | Department of Computer Science and Communication Engineering, Kyushu University |
| Date | 1998/3/5 |
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| Volume (vol) | vol.97 |
| Number (no) | 576 |
| Page | pp.pp.- |
| #Pages | 8 |
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