| Presentation | 1997/10/29 A Hierarchical Floorplanning Method using Genetic Algorithm Chiaki SUGIMOTO, Takashi SHIMAMOTO, Akio SAKAMOTO, Hiroyuki SUZUKI, Hiroomi ANZAI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In the stage of floorplanning of LSI design, it is generally hard to estimate the final area of chip strictly. We propose an evaluation method for a given relative positions of the modules. It estimates the final chip area as accurate as possible by considering the width of routing channels from the interconnection information among the modules. We assume a hierarchical floorplan model; a chip consists of some regions which consist of some soft and/or hard blocks, and finally soft blocks consist of some standard cells. To obtain a floorpllan with minimal chip area we use genetic algorithms. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | hierarchical floorplan / region / block / cell / genetic algorithm |
| Paper # | VLD97-96 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1997/10/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Hierarchical Floorplanning Method using Genetic Algorithm |
| Sub Title (in English) | |
| Keyword(1) | hierarchical floorplan |
| Keyword(2) | region |
| Keyword(3) | block |
| Keyword(4) | cell |
| Keyword(5) | genetic algorithm |
| 1st Author's Name | Chiaki SUGIMOTO |
| 1st Author's Affiliation | Faculty of Engineering, Tokushima University() |
| 2nd Author's Name | Takashi SHIMAMOTO |
| 2nd Author's Affiliation | Faculty of Engineering, Tokushima University |
| 3rd Author's Name | Akio SAKAMOTO |
| 3rd Author's Affiliation | Department of Information Systems Engineering, Kochi University of Technology |
| 4th Author's Name | Hiroyuki SUZUKI |
| 4th Author's Affiliation | Hitachi Microcomputer System LTD. |
| 5th Author's Name | Hiroomi ANZAI |
| 5th Author's Affiliation | Hitachi Microcomputer System LTD. |
| Date | 1997/10/29 |
| Paper # | VLD97-96 |
| Volume (vol) | vol.97 |
| Number (no) | 344 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |