| Presentation | 1997/10/29 A Module Generator for Embedded DRAM Macros Hideki Takeuchi, Tomoaki Yabe, Shinji Miyano, Takehiko Hojyo, Masaaki Tazawa, Motohiro Enkaku, Masaaki Yamada, Masami Murakata, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | It is possible to integrate logic circuits and memory macro such as DRAM in one chip for a recent semiconductor process technology advancement. The authors have been developed DRAM macros which is embedded as an ASIC macro cell. This paper describes an expandable architecture and a method to generate the layouts of DRAM macros using module generator. Especially it describes an algorithm for connection in decoder. And it describes a unified macro testing scheme. The experimental results demonstrate the efficiency and effectiveness of the algorithm. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | embedded / DRAM / macro / ASIC / module generator / metal option |
| Paper # | VLD97-94 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
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| Conference Date | 1997/10/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Module Generator for Embedded DRAM Macros |
| Sub Title (in English) | |
| Keyword(1) | embedded |
| Keyword(2) | DRAM |
| Keyword(3) | macro |
| Keyword(4) | ASIC |
| Keyword(5) | module generator |
| Keyword(6) | metal option |
| 1st Author's Name | Hideki Takeuchi |
| 1st Author's Affiliation | Semiconductor DA & Test Engineering Center, Toshiba Corporation() |
| 2nd Author's Name | Tomoaki Yabe |
| 2nd Author's Affiliation | ULSI Device Engineering Laboratory, Toshiba Corporation |
| 3rd Author's Name | Shinji Miyano |
| 3rd Author's Affiliation | ULSI Device Engineering Laboratory, Toshiba Corporation |
| 4th Author's Name | Takehiko Hojyo |
| 4th Author's Affiliation | Semiconductor System Engineering Center, Toshiba Corporation |
| 5th Author's Name | Masaaki Tazawa |
| 5th Author's Affiliation | Toshiba Information Systems Corporation |
| 6th Author's Name | Motohiro Enkaku |
| 6th Author's Affiliation | Semiconductor System Engineering Center, Toshiba Corporation |
| 7th Author's Name | Masaaki Yamada |
| 7th Author's Affiliation | Semiconductor DA & Test Engineering Center, Toshiba Corporation |
| 8th Author's Name | Masami Murakata |
| 8th Author's Affiliation | Semiconductor DA & Test Engineering Center, Toshiba Corporation |
| Date | 1997/10/29 |
| Paper # | VLD97-94 |
| Volume (vol) | vol.97 |
| Number (no) | 344 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |