Presentation 1997/10/29
Module Selection Using Manufacturing Information
Hiroyuki Tomiyama, Hiroto Yasuura,
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Abstract(in English) Due to disturbances of manufacturing processes, different LSI chips with the same design possibly have different propagation delays. However, such manufacturing disturbances are rarely considered in high-level design phases. This paper addresses a module selection problem in high-level synthesis. This paper assumes the probabilistic nature of propagation delays of functional units caused by the manufacturing disturbances. The objective of the module selection problem is minimization of the cost per faultless chip. This paper describes two significant theorems on module selection which help to prune the design space to be explored without the loss of the optimality. Based on the theorems, a module selection algorithm is proposed. Experimental results demonstrate that the proposed algorithm finds the optimal module selection which would not have been explored without the manufacturing information.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) High-Level Synthesis / Module Selection / Manufacturing Processes / Uncertain Delays
Paper # VLD97-93
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Committee VLD
Conference Date 1997/10/29(1days)
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Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Module Selection Using Manufacturing Information
Sub Title (in English)
Keyword(1) High-Level Synthesis
Keyword(2) Module Selection
Keyword(3) Manufacturing Processes
Keyword(4) Uncertain Delays
1st Author's Name Hiroyuki Tomiyama
1st Author's Affiliation Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University()
2nd Author's Name Hiroto Yasuura
2nd Author's Affiliation Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University
Date 1997/10/29
Paper # VLD97-93
Volume (vol) vol.97
Number (no) 344
Page pp.pp.-
#Pages 8
Date of Issue