| Presentation | 1997/10/29 Implementation of Test Pattern Generation and Control Circuits in Memory Burn-In Testers by using FPGAs Yukihiro IGUCHI, Tomoomi KISHINO, Haruo YOKOYAMA, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | It is desired to develop a flexible burn-in tester adaptable for various kinds of memories and their tests. Such a flexible tester can be cost-effectively realized by using reconfigurable FPGAs for the electric parts. We implemented the pattern generation and control circuits using FPGAs to show its feasiblity. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Memory / Burn-in tester |
| Paper # | VLD97-85 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
|---|---|
| Conference Date | 1997/10/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of Test Pattern Generation and Control Circuits in Memory Burn-In Testers by using FPGAs |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Memory |
| Keyword(3) | Burn-in tester |
| 1st Author's Name | Yukihiro IGUCHI |
| 1st Author's Affiliation | Dept. of Computer Science Meiji University() |
| 2nd Author's Name | Tomoomi KISHINO |
| 2nd Author's Affiliation | Technical Center Japan Engineering CO., LTD. |
| 3rd Author's Name | Haruo YOKOYAMA |
| 3rd Author's Affiliation | Technical Center Japan Engineering CO., LTD. |
| Date | 1997/10/29 |
| Paper # | VLD97-85 |
| Volume (vol) | vol.97 |
| Number (no) | 344 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |