| Presentation | 1997/10/29 Full-Scan Testing on Boards with The Boundary-Scan Technique Yasunori Sameshima, Tomoo Fukazawa, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Board test requires interconnect test between LSI chips and internal logic test of the chips on the board. The former has been facilitated using chips designed based on the IEEE 1149.1 standard (Boundary-Scan-BS), however, it has been difficult to establish a systematic method to test the internal logic of the chips on the board because it depends on the test circuits in the chips. We developed a board test pattern generation system not only for the interconnect test but also for the internal logic test using a full-scan test pattern for the chip. This paper explains how to generate the board test pattern from the full-scan test pattern for the chip. That is, 1) how to map a test pattern for external pins of the chip to the BS register, 2) how to avoid bus conflicts on the board by BS instructions and 3) how to translate the full-scan test pattern for board testing based on TAP (Test Access Port) controller state transition. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Boundary-Scan / IEEE standard / board test / full-scan test / TAP controller |
| Paper # | VLD97-80 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1997/10/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Full-Scan Testing on Boards with The Boundary-Scan Technique |
| Sub Title (in English) | |
| Keyword(1) | Boundary-Scan |
| Keyword(2) | IEEE standard |
| Keyword(3) | board test |
| Keyword(4) | full-scan test |
| Keyword(5) | TAP controller |
| 1st Author's Name | Yasunori Sameshima |
| 1st Author's Affiliation | NTT Optical Network Systems Laboratories() |
| 2nd Author's Name | Tomoo Fukazawa |
| 2nd Author's Affiliation | NTT Optical Network Systems Laboratories |
| Date | 1997/10/29 |
| Paper # | VLD97-80 |
| Volume (vol) | vol.97 |
| Number (no) | 344 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |