Presentation 1997/6/26
Low Power Dissipation of High-Performance VLSI Processor for State-Space Digital Filters
Michiru Iwawaki, Yoshitaka Tsunekawa, Mamoru Miura,
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Abstract(in English) This paper presents a low power dissipation architecture for our proposed VLSI processor of state-space digital filters using distributed arithmetic. To reduce power dissipation, we replace ROM using in usual distributed arithmetic with optimal circuits of logical gates. In addition, by applying the properties of filter structures to optimal functional circuits, a more decrease in power dissipation becomes possible. As a result, high-performance VLSI processor is implemented, which has very high sampling rate of 3.7MHz (0.6μm CMOS technology) and low power dissipation of about 2.73W in the case where the filter order is 16. This can decrease power dissipation to about 75% when compared to the VLSI processor using ROM.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) state-space digital filters / distributed arithmetic / low power dissipation / filter structure
Paper # CAS97-9
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Conference Information
Committee VLD
Conference Date 1997/6/26(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Low Power Dissipation of High-Performance VLSI Processor for State-Space Digital Filters
Sub Title (in English)
Keyword(1) state-space digital filters
Keyword(2) distributed arithmetic
Keyword(3) low power dissipation
Keyword(4) filter structure
1st Author's Name Michiru Iwawaki
1st Author's Affiliation Faculty of Engieering, Iwate University()
2nd Author's Name Yoshitaka Tsunekawa
2nd Author's Affiliation Faculty of Engieering, Iwate University
3rd Author's Name Mamoru Miura
3rd Author's Affiliation Faculty of Engieering, Iwate University
Date 1997/6/26
Paper # CAS97-9
Volume (vol) vol.97
Number (no) 138
Page pp.pp.-
#Pages 8
Date of Issue