| Presentation | 1996/10/17 Programmable Design for Memory Sharing Processor Array (MSPA) Dongju Li, Hiroaki Kunieda, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Memory sharing processor array (MSPA) architecture has been proposed with advantages of high efficient parallel processing, less data storage requirement, and high cost performance. MSPA design methodology has been developed with regularity structure and systematic procedure. In this paper, programmable MSPA is proposed to embed not only MSPA architecture, but design procedure into silicon chip so that various applications can be performed with excellently high speed. MSPA controller schedules operations corresponding to algorithm size, allocates resources altomaticaly, manipulates data flow among I/O ports, memory and processing elements (PEs). The introduction of this controller lead to a possibility to realize programmable and reconfigurable MSPA chip design. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | parallel processing / interconnection / memory address generation / array processor architecture. |
| Paper # | VLD96-52 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 1996/10/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Programmable Design for Memory Sharing Processor Array (MSPA) |
| Sub Title (in English) | |
| Keyword(1) | parallel processing |
| Keyword(2) | interconnection |
| Keyword(3) | memory address generation |
| Keyword(4) | array processor architecture. |
| 1st Author's Name | Dongju Li |
| 1st Author's Affiliation | Dept. of EE Eng. Tokyo Institute of Technology() |
| 2nd Author's Name | Hiroaki Kunieda |
| 2nd Author's Affiliation | Dept. of EE Eng. Tokyo Institute of Technology |
| Date | 1996/10/17 |
| Paper # | VLD96-52 |
| Volume (vol) | vol.96 |
| Number (no) | 298 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |